1. Field of the Invention
The present invention relates to a method for fabrication of a semiconductor device and, more particularly, to a method for fabrication of a semiconductor device having a porous insulating film.
2. Description of the Related Art
Recent semiconductor devices with a higher degree of integration and scale down than before pose a serious problem with delay of electric signals resulting from the time constant of wiring. This problem is addressed by making the wiring of multi-layer structure from low-resistance copper (Cu) in place of aluminum (Al). Unfortunately, copper hardly undergoes dry etching for patterning unlike any other metallic materials, such as aluminum, which are used for the multi-layer wiring structure in the past. This disadvantage is overcome by employing the damascene method, which consists of forming wiring grooves in an insulating film and embedding a copper film in the wiring groove, thereby forming the wiring pattern.
The foregoing steps can be achieved more efficiently by the dual-damascene method, which consists of forming via holes and wiring grooves and then embedding copper therein simultaneously. This method is attracting attention because it effectively reduces the number of steps.
Highly integrated semiconductor devices are subject to slow-down due to increased capacity between wirings; therefore, they inevitably need fine multi-layer wirings, with the capacity between wirings kept low by interlayer insulating film of so-called low-dielectric material. Examples of such materials include fluorine-containing silicon oxide (FSG) having a dielectric constant of about 3.5, organic polymers typified by polyarylether (PAE), and inorganic silicon compounds typified by carbon-containing silicon oxide (SiOC), hydrogen silsesquioxane (HSQ), and methyl silsesquioxane (MSQ), which have a lower dielectric constant than silicon oxide. Moreover, attempts are being made to further reduce their dielectric constant to about 2.3 by making them porous.
The dual-damascene method mentioned above is applied to the interlayer insulating film having a low dielectric constant by the steps of forming a film of inorganic material (SiOC) on the substrate by chemical vapor deposition (CVD) process, forming a film of organic material (PAE) on the inorganic film by coating, forming wiring grooves in the organic film by etching, and forming via holes in the inorganic film. The thus formed layer structure has an interface between the inorganic film and the organic film and hence permits etching to be performed under good control with a high etching selective ratio of the former to the latter. (See Japanese Patent Laid-Open No. 2004-63859, for instance).
Moreover, CVD process to form the inorganic film can readily adapt itself to varied conditions (gas flow rate and RF power) to cope with fluctuation of film quality, and CVD process usually gives rise to a compact film with high mechanical strength.